[all-commits] [llvm/llvm-project] f3a725: [RISCV] Add signext test for llvm.abs.i32 for rv64...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3a725af43b34df227745d7f8c531f4751d7a37c
      https://github.com/llvm/llvm-project/commit/f3a725af43b34df227745d7f8c531f4751d7a37c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-05 (Sat, 05 Feb 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Add signext test for llvm.abs.i32 for rv64 Zbb.

This shows that we don't preserve sign bits across the
abs expansion, but I think we could if we used negw+max.