[all-commits] [llvm/llvm-project] 673d68: [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -...

Craig Topper via All-commits all-commits at lists.llvm.org
Sat Feb 5 12:50:22 PST 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 673d68cd923a9daa5065b929453bf4a4b8d39650
      https://github.com/llvm/llvm-project/commit/673d68cd923a9daa5065b929453bf4a4b8d39650
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-05 (Sat, 05 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll

  Log Message:
  -----------
  [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).

Add a new ISD opcode to represent the sign extending behavior of
vmv.x.h. Keep the previous anyext opcode to allow the existing
(fmv_x_anyexth (fmv_h_x X)) combine to keep working without needing
to generate a sign extend.

For fmv.x.w we are able to match the sext_inreg in an isel pattern,
but a 16-bit sext_inreg is lowered to a shift pair before isel. This
seemed like a larger match than we should do in isel.

Differential Revision: https://reviews.llvm.org/D118974


  Commit: d1899da3a2c5139cd4065e7a0dac4a26b3238547
      https://github.com/llvm/llvm-project/commit/d1899da3a2c5139cd4065e7a0dac4a26b3238547
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-05 (Sat, 05 Feb 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll

  Log Message:
  -----------
  [RISCV] Add more tests for rotate idioms. Add more RUN lines. NFC

We were only testing rotate idioms on rv32i. DAGCombiner won't
form ISD::ROTL/ROTR unless those operations are Legal or Custom.
They aren't for rv32 so we were only testing shift lowering.

This commit adds i64 idioms and the idioms that mask the shift
amount to avoid UB for a rotate of 0. I've added riscv64 and Zbb
RUN lines to show that we do match rotate for XLen types when
available. We currently miss i32 on rv64izbb.


Compare: https://github.com/llvm/llvm-project/compare/7c675923c739...d1899da3a2c5


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