[all-commits] [llvm/llvm-project] d752ea: [RISCV] Remove exclusions for zext.h/zext.w from o...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d752ea9a7235cb0fe677517129e66b1935ae5285
      https://github.com/llvm/llvm-project/commit/d752ea9a7235cb0fe677517129e66b1935ae5285
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-04 (Fri, 04 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll

  Log Message:
  -----------
  [RISCV] Remove exclusions for zext.h/zext.w from our (and (srl X, C1), C2) selection code.

This code tries to replace the pattern with a pair of shifts, but
we were excluding if the And could be a zext.h or zext.w. The SLLI/SRL
pair is more compressible and doesn't come with much down side.

We do regress one test case in rv64i-exhaustive-w-insts.ll but we
can probably add a narrower exclusion for that case.