[all-commits] [llvm/llvm-project] 1d8bbe: [RISCV] Implement a basic version of AArch64Redund...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1d8bbe3d255ff5fa3e0049922398f7e2f3662827
      https://github.com/llvm/llvm-project/commit/1d8bbe3d255ff5fa3e0049922398f7e2f3662827
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-04 (Fri, 04 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCV.h
    A llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

  Log Message:
  -----------
  [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.

Using AArch64's original implementation for reference, this patch
implements a pass to remove unneeded copies of X0. This pass runs
after register allocation and looks to see if a register is implied
to be 0 by a branch in the predecessor basic block.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118160