[all-commits] [llvm/llvm-project] 997a86: [RISCV] Remove createVirtualRegister from RISCVIns...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 997a86b99cd67de99385dc72c384cdae326d26f6
      https://github.com/llvm/llvm-project/commit/997a86b99cd67de99385dc72c384cdae326d26f6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-03 (Thu, 03 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [RISCV] Remove createVirtualRegister from RISCVInstrInfo::movImm.

Based on the discussion in D61884, this was done to enable compressed
instructions by giving freedom to pick a compressible register.

Integer materializing can generate LUI, ADDI, ADDIW, SLLI and some
Zb* instructions. C.LI, C.LUI, C.ADDI, C.ADDIW, and C.SLLI all have a 5-bit
register encoding. The Zb* instructions aren't compressible. Based on
that I don't think compressibility of the register is a concern.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118741