[all-commits] [llvm/llvm-project] 005fd8: [RISCV] Add support for Zihintpause extention

[Shao-Ce SUN via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 005fd8aa702edbc532763038365575da96e5787d
      https://github.com/llvm/llvm-project/commit/005fd8aa702edbc532763038365575da96e5787d
  Author: Shao-Ce SUN <shaoce at nj.iscas.ac.cn>
  Date:   2022-02-03 (Thu, 03 Feb 2022)

  Changed paths:
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/attributes.ll
    R llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt
    M llvm/test/MC/RISCV/rv32i-invalid.s
    A llvm/test/MC/RISCV/rv32zihintpause-valid.s
    A llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Add support for Zihintpause extention

Add support for the 'pause' hint instruction as an alias for
'fence w, 0'. To do this allow the 'fence' operands pred and succ
to be set to 0 (the empty set). This will also allow future hints
to be encoded as 'fence 0, <x>' and 'fence <x>, 0'.

This patch revised from @mundaym's D93019.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D117789