[all-commits] [llvm/llvm-project] 11cf80: [AArch64][CodeGen] Always use SVE (when enabled) t...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 11cf80779654f90faa4e44bda24c7eab049c4a3b
      https://github.com/llvm/llvm-project/commit/11cf80779654f90faa4e44bda24c7eab049c4a3b
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-02-02 (Wed, 02 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

  Log Message:
  -----------
  [AArch64][CodeGen] Always use SVE (when enabled) to lower integer divides

This patch adds custom lowering support for ISD::SDIV and ISD::UDIV
when SVE is enabled, regardless of the minimum SVE vector length. We do
this because NEON simply does not have vector integer divide support, so
we want to take advantage of these instructions in SVE.

As part of this patch I've also simplified LowerToPredicatedOp to avoid
re-asking the same question about whether we should be using SVE for
fixed length vectors. Once we've made the decision to call
LowerToPredicatedOp, then we should simply assert we should be using SVE.

I've updated the 128-bit min SVE vector bits tests here:

  CodeGen/AArch64/sve-fixed-length-int-div.ll
  CodeGen/AArch64/sve-fixed-length-int-rem.ll

Differential Revision: https://reviews.llvm.org/D117871