[all-commits] [llvm/llvm-project] 0d6e64: [PowerPC] Update P10 vector insert patterns to use...

[Amy Kwan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d6e64755acf0334f9a3958c254b32ac95aa859b
      https://github.com/llvm/llvm-project/commit/0d6e64755acf0334f9a3958c254b32ac95aa859b
  Author: Amy Kwan <amy.kwan1 at ibm.com>
  Date:   2022-02-01 (Tue, 01 Feb 2022)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
    M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

  Log Message:
  -----------
  [PowerPC] Update P10 vector insert patterns to use refactored load/stores, and update handling of v4f32 vector insert.

This patch updates the P10 patterns with a load feeding into an insertelt to
utilize the refactored load and store infrastructure, as well as updating any
tests that exhibit any codegen changes.

Furthermore, custom legalization is added for v4f32 on Power9 and above to not
only assist with adjusting the refactored load/stores for P10 vector insert,
but also it enables the utilization of direct moves.

Differential Revision: https://reviews.llvm.org/D115691