[all-commits] [llvm/llvm-project] 78fd41: [AArch64][GlobalISel] CodeGen for Armv8.8/9.3 MOPS

[tyb0807 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78fd413cf736953ac623cabf3d5f84c8219e31f8
      https://github.com/llvm/llvm-project/commit/78fd413cf736953ac623cabf3d5f84c8219e31f8
  Author: tyb0807 <sontuan.vu at arm.com>
  Date:   2022-01-31 (Mon, 31 Jan 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
    M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
    A llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
    A llvm/test/CodeGen/AArch64/aarch64-mops.ll
    M llvm/unittests/Target/AArch64/InstSizes.cpp

  Log Message:
  -----------
  [AArch64][GlobalISel] CodeGen for Armv8.8/9.3 MOPS

This implements codegen for Armv8.8/9.3 Memory Operations extension (MOPS).
Any memcpy/memset/memmov intrinsics will always be emitted as a series
of three consecutive instructions P, M and E which perform the
operation. The SelectionDAG implementation is split into a separate
patch.

AArch64LegalizerInfo will now consider the following generic opcodes
if +mops is available, instead of legalising by expanding them to
libcalls: G_BZERO, G_MEMCPY_INLINE, G_MEMCPY, G_MEMMOVE, G_MEMSET
The s8 value of memset is legalised to s64 to match the pseudos.

AArch64O0PreLegalizerCombinerInfo will still be able to combine
G_MEMCPY_INLINE even if +mops is present, as it is unclear whether it is
better to generate fixed length copies or MOPS instructions for the
inline code of small or zero-sized memory operations, so we choose to be
conservative for now.

AArch64InstructionSelector will select the above as new pseudo
instructions: AArch64::MOPSMemory{Copy/Move/Set/SetTagging} These are
each expanded to a series of three instructions (e.g. SETP/SETM/SETE)
which must be emitted together during code emission to avoid scheduler
reordering.

This is part 3/4 of a series of patches split from
https://reviews.llvm.org/D117405 to facilitate reviewing.

Patch by Tomas Matheson and Son Tuan Vu

Differential Revision: https://reviews.llvm.org/D117763