[all-commits] [llvm/llvm-project] 127667: [RISCV] Improve extract_vector_elt for fixed mask ...

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1276678982a0c9d0d7aba6afdc83d34ee42f397c
      https://github.com/llvm/llvm-project/commit/1276678982a0c9d0d7aba6afdc83d34ee42f397c
  Author: jacquesguan <Jianjian.Guan at streamcomputing.com>
  Date:   2022-01-29 (Sat, 29 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

  Log Message:
  -----------
  [RISCV] Improve extract_vector_elt for fixed mask registers.

Now the backend promotes mask vector to an i8 vector and extract element from that. We could bitcast to a widen element vector, and extract from it to GPR, then use I instruction to extract the certain bit.

Differential Revision: https://reviews.llvm.org/D117389