[all-commits] [llvm/llvm-project] 6d6c44: [RISCV] Add support for matching vwmulsu from fixe...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6d6c44a3f36f4854a567cbb2e1259a91ee0915ee
      https://github.com/llvm/llvm-project/commit/6d6c44a3f36f4854a567cbb2e1259a91ee0915ee
  Author: Chenbing.Zheng <Chenbing.Zheng at streamcomputing.com>
  Date:   2022-01-28 (Fri, 28 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll

  Log Message:
  -----------
  [RISCV] Add support for matching vwmulsu from fixed vectors

According to riscv-v-spec-1.0, widening signed(vs2)-unsigned integer multiply
vwmulsu.vv vd, vs2, vs1, vm # vector-vector
vwmulsu.vx vd, vs2, rs1, vm # vector-scalar

It is worth noting that signed op is only for vs2.
For vwmulsu.vv, we can swap two ops, and don't care which is sign extension,
but for vwmulsu.vx signExt can not be a vector extended from scalar (rs1).
I specifically added two functions ending with _swap in the test case.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D118215