[all-commits] [llvm/llvm-project] e900f0: [BOLT] Fix AARCH64 registers aliasing

[Vladislav Khmelevsky via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e900f0584e904e884207e40c80a8126824ef4c41
      https://github.com/llvm/llvm-project/commit/e900f0584e904e884207e40c80a8126824ef4c41
  Author: Vladislav Khmelevsky <och95 at yandex.ru>
  Date:   2022-01-28 (Fri, 28 Jan 2022)

  Changed paths:
    M bolt/lib/Core/MCPlusBuilder.cpp
    M bolt/unittests/CMakeLists.txt
    A bolt/unittests/Core/CMakeLists.txt
    A bolt/unittests/Core/MCPlusBuilder.cpp

  Log Message:
  -----------
  [BOLT] Fix AARCH64 registers aliasing

The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7.
Using the downwards propagation this register will become a super
register for all X0..X7 and its super registers which is not right. This
patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator.

Vladislav Khmelevsky,
Advanced Software Technology Lab, Huawei

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D117394