[all-commits] [llvm/llvm-project] 70e1cc: [RISCV] Prefer vmslt.vx v0, v8, zero over vmsle.vi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 70e1cc67926dc43a4860156ea3755cebcf97fc09
      https://github.com/llvm/llvm-project/commit/70e1cc67926dc43a4860156ea3755cebcf97fc09
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-27 (Thu, 27 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll

  Log Message:
  -----------
  [RISCV] Prefer vmslt.vx v0, v8, zero over vmsle.vi v0, v8, -1.

At least when starting from a vmslt.vx intrinsic or ISD::SETLT. We
don't handle the case where the user used vmsle.vx intrinsic with -1.