[all-commits] [llvm/llvm-project] af1c8f: [AArch64][SVE] Folds VSELECT if the predicate is a...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af1c8f0d142179826197f22c3880c980e6e47b3d
      https://github.com/llvm/llvm-project/commit/af1c8f0d142179826197f22c3880c980e6e47b3d
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2022-01-27 (Thu, 27 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    A llvm/test/CodeGen/AArch64/sve-vselect-fold.ll

  Log Message:
  -----------
  [AArch64][SVE] Folds VSELECT if the predicate is all active.

This adds the following changes:

* Fold: vselect(<all active predicate>, x, y) => x
* Extend isAllActivePredicate to take vscale_range into account, e.g.
  isAllActivePredicate(vl16) for nxv16i1 and vscale == 1 => true.
  isAllActivePredicate(vl32) for nxv16i1 and vscale == 2 => true.

Differential Revision: https://reviews.llvm.org/D118147