[all-commits] [llvm/llvm-project] 33185e: [mlir] Add ODS support for enum attributes with gr...

[Jeremy Furtek via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 33185e66f24187e9573154090556967f71265b7c
      https://github.com/llvm/llvm-project/commit/33185e66f24187e9573154090556967f71265b7c
  Author: Jeremy Furtek <jfurtek at nvidia.com>
  Date:   2022-01-26 (Wed, 26 Jan 2022)

  Changed paths:
    M mlir/docs/OpDefinitions.md
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
    M mlir/include/mlir/Dialect/Vector/VectorOps.td
    M mlir/include/mlir/IR/OpBase.td
    M mlir/tools/mlir-tblgen/EnumsGen.cpp
    M mlir/unittests/TableGen/EnumsGenTest.cpp
    M mlir/unittests/TableGen/enums.td

  Log Message:
  -----------
  [mlir] Add ODS support for enum attributes with grouped bit cases

This diff modifies the tablegen specification and code generation for
BitEnumAttr attributes in MLIR Operation Definition Specification (ODS) files.
Specifically:

- there is a new tablegen class for "none" values (i.e. no bits set)
- single-bit enum cases are specified via bit index (i.e. [0, 31]) instead of
  the resulting enum integer value
- there is a new tablegen class to represent a "grouped" bitwise OR of other
  enum values

This diff is intended as an initial step towards improving "fastmath"
optimization support in MLIR, to allow more precise control of whether certain
floating point optimizations are applied in MLIR passes. "Fast" math options
for floating point MLIR operations would (following subsequent RFC and
discussion) be specified by using the improved enum bit support in this diff.
For example, a "fast" enum value would act as an alias for a group of other
cases (e.g. finite-math-only, no-signed-zeros, etc.), in a way that is similar
to support in C/C++ compilers (clang, gcc).

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D117029