[all-commits] [llvm/llvm-project] d70d99: [x86] add test for miscompile from wrong min signb...

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d70d9977999b8a08fe5635fb2c58588e6ffb7997
      https://github.com/llvm/llvm-project/commit/d70d9977999b8a08fe5635fb2c58588e6ffb7997
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-01-26 (Wed, 26 Jan 2022)

  Changed paths:
    M llvm/test/CodeGen/X86/vselect-constants.ll

  Log Message:
  -----------
  [x86] add test for miscompile from wrong min signbits ( #53401 ); NFC


  Commit: 63daea8b35cdb48d6061dc8ad72e5445b808dbce
      https://github.com/llvm/llvm-project/commit/63daea8b35cdb48d6061dc8ad72e5445b808dbce
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-01-26 (Wed, 26 Jan 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/vselect-constants.ll

  Log Message:
  -----------
  [SDAG] fix bug in ComputeNumSignBits of target constant

The loop below the changed line assumes that the element
width of the target constant is the same as the element
width of the loaded value, but that is not always true.

We could try harder to do some kind of min/max calc even
if the sizes don't match, but that can be another patch
if needed. This fixes #53401 (miscompile) and does not
change the motivating cases added when this analysis
was introduced:
ad298f86b7ad2a


Compare: https://github.com/llvm/llvm-project/compare/ef8206320769...63daea8b35cd