[all-commits] [llvm/llvm-project] 0776f6: [LSV] Vectorize loads of vectors by turning it int...

[Benjamin Kramer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0776f6e04d8c3823c31b8fa6fa7d1376a7009af1
      https://github.com/llvm/llvm-project/commit/0776f6e04d8c3823c31b8fa6fa7d1376a7009af1
  Author: Benjamin Kramer <benny.kra at googlemail.com>
  Date:   2022-01-26 (Wed, 26 Jan 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
    M llvm/test/CodeGen/AMDGPU/fshl.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/memory_clause.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/mul_int24.ll
    M llvm/test/CodeGen/AMDGPU/sdiv.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/select-vectors.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    A llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll

  Log Message:
  -----------
  [LSV] Vectorize loads of vectors by turning it into a larger vector

Use shufflevector to do the subvector extracts. This allows a lot more
load merging on AMDGPU and also on NVPTX when <2 x half> is involved.

Differential Revision: https://reviews.llvm.org/D117219