[all-commits] [llvm/llvm-project] c5263c: Restrict performPostLD1Combine to 64 and 128 bit v...

[Andrzej Warzyński via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c5263cd518689bc17690b90aa6bb0a163ef4a56c
      https://github.com/llvm/llvm-project/commit/c5263cd518689bc17690b90aa6bb0a163ef4a56c
  Author: Maciej Gabka <maciej.gabka at arm.com>
  Date:   2022-01-26 (Wed, 26 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll

  Log Message:
  -----------
  Restrict performPostLD1Combine to 64 and 128 bit vectors

When wider vectors are used, for example fixed width SVE,
there is no patterns to select AArch64ISD::LD1LANEpost
nodes, so we should do an early exit.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D117674