[all-commits] [llvm/llvm-project] 970a19: [Clang][RISCV] Guard vmulh, vsmul correctly

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 970a191203e6d3d34c873beb64c333f2890b2025
      https://github.com/llvm/llvm-project/commit/970a191203e6d3d34c873beb64c333f2890b2025
  Author: eopXD <eop.chen at sifive.com>
  Date:   2022-01-25 (Tue, 25 Jan 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul-eew64.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul-eew64.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vmul-eew64.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul-eew64.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c
    M clang/utils/TableGen/RISCVVEmitter.cpp

  Log Message:
  -----------
  [Clang][RISCV] Guard vmulh, vsmul correctly

According to v-spec 1.0, `vmulh`, `vmulhu`, `vmulhsu` and `vsmul` are
NOT supported for EEW=64 in Zve64*.

This patch tries to guard it correctly.

Authored by: Craig Topper <craig.topper at sifive.com> @craig.topper
Co-Authored by: Eop Chen <eop.chen at sifive.com> @eopXD

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117913