[all-commits] [llvm/llvm-project] 9aaa74: [RISCV] Add patterns of SET[U]LT_VI for STECC forms

[ZCBing via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9aaa74aeeff37b85e29369287ee94773e699b8b7
      https://github.com/llvm/llvm-project/commit/9aaa74aeeff37b85e29369287ee94773e699b8b7
  Author: Chenbing.Zheng <Chenbing.Zheng at streamcomputing.com>
  Date:   2022-01-24 (Mon, 24 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

  Log Message:
  -----------
  [RISCV] Add patterns of SET[U]LT_VI for STECC forms

This patch optmizes "li a0, 5
                     vmsgt[u].vx v10, v8, a0"
                 -> "vmsgt[u].vi v10, v8, 5"

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D118014