[all-commits] [llvm/llvm-project] 0b7997: [RISCV] Merge some rvv intrinsic test cases that o...
Craig Topper via All-commits
all-commits at lists.llvm.org
Sun Jan 23 09:41:58 PST 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 0b799791807e6b23a568526484f6cdaf0984cf02
https://github.com/llvm/llvm-project/commit/0b799791807e6b23a568526484f6cdaf0984cf02
Author: Craig Topper <craig.topper at sifive.com>
Date: 2022-01-23 (Sun, 23 Jan 2022)
Changed paths:
R llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfadd.ll
R llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfclass.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
R llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
R llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
R llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmax.ll
R llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
R llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmin.ll
R llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
R llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
R llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmul.ll
R llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
R llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
R llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
R llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
R llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
R llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
R llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
R llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfredusum-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
R llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
R llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
R llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
R llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
R llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
R llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
R llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
R llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
R llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfsub.ll
R llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
R llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
R llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
R llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
R llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
R llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
R llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
R llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
R llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
R llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
R llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
R llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
Log Message:
-----------
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
Instead of having a test for i32 XLen and i64 XLen, use sed to
replace iXLen with i32/i64 before running llc.
This change covers all of the floating point tests.
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