[all-commits] [llvm/llvm-project] 85e42d: [RISCV] Merge some rvv intrinsic test cases that o...

Craig Topper via All-commits all-commits at lists.llvm.org
Sat Jan 22 22:17:18 PST 2022 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 85e42db1b6db16a2dab4405604971d84899612bf
      https://github.com/llvm/llvm-project/commit/85e42db1b6db16a2dab4405604971d84899612bf
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-22 (Sat, 22 Jan 2022)

  Changed paths:
    R llvm/test/CodeGen/RISCV/rvv/vcpop-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vcpop-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vcpop.ll
    R llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfirst.ll
    R llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vid.ll
    R llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/viota.ll
    R llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vlm.ll
    R llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmand.ll
    R llvm/test/CodeGen/RISCV/rvv/vmandn-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmandn-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmandn.ll
    R llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmclr.ll
    R llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmnand.ll
    R llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmnor.ll
    R llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmor.ll
    R llvm/test/CodeGen/RISCV/rvv/vmorn-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmorn-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmorn.ll
    R llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmset.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsif.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsof.ll
    R llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
    R llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmxor.ll
    R llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsm.ll

  Log Message:
  -----------
  [RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.

Instead of having a test for i32 XLen and i64 XLen, use sed to
replace iXLen with i32/i64 before running llc.

This change updates tests for intrinsics that operate exclusively
on mask values. It removes over 4000 lines worth of test content.
More merging will come in future changes.

Differential Revision: https://reviews.llvm.org/D117968


  Commit: be6070c290e23d659c6374284a632442e2360967
      https://github.com/llvm/llvm-project/commit/be6070c290e23d659c6374284a632442e2360967
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-22 (Sat, 22 Jan 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

  Log Message:
  -----------
  [RISCV] Use FP ABI for some RVV intrinsic tests. NFC

Removes moves from GPR to FPR and improves f64 tests on RV32.

Differential Revision: https://reviews.llvm.org/D117969


Compare: https://github.com/llvm/llvm-project/compare/3cf15af2daa9...be6070c290e2

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