[all-commits] [llvm/llvm-project] 7b3d30: [RISCV] Add isel patterns for grevi, shfli, and un...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b3d30728816403d1fd73cc5082e9fb761262bce
      https://github.com/llvm/llvm-project/commit/7b3d30728816403d1fd73cc5082e9fb761262bce
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-20 (Thu, 20 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns for grevi, shfli, and unshfli to brev8/zip/unzip instructions.

Zbkb supports some encodings of the general grevi, shfli, and
unshfli instructions legal, so we added separate instructions for
those encodings to improve the diagnostics for assembler and
disassembler. To be consistent we should always use these separate
instructions whenever those specific encodings of grevi/shfli/unshfli
occur. So this patch adds specific isel patterns to override the generic
isel patterns for these cases. Similar was done for rev8 and zext.h
for Zbb previously.