[all-commits] [llvm/llvm-project] 7a275d: [RISCV] Remove Zvlsseg extension.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7a275dc35411b8c3f510166f40c225cd10dc5eec
      https://github.com/llvm/llvm-project/commit/7a275dc35411b8c3f510166f40c225cd10dc5eec
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-20 (Thu, 20 Jan 2022)

  Changed paths:
    M clang/include/clang/Basic/RISCVVTypes.def
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M clang/utils/TableGen/RISCVVEmitter.cpp
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch-invalid.s
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/rvv/zvlsseg.s

  Log Message:
  -----------
  [RISCV] Remove Zvlsseg extension.

This string no longer appears in the Vector Extension specification.
The segment load/store instructions are just part of the vector
instruction set.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D117724