[all-commits] [llvm/llvm-project] 94e69f: [RISCV] Add DAG combine to fold (fp_to_int_sat (ff...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 94e69fbb4f3a9719d4d8cc7268dd5db5d0be7e8f
      https://github.com/llvm/llvm-project/commit/94e69fbb4f3a9719d4d8cc7268dd5db5d0be7e8f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-20 (Thu, 20 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    A llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    A llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to fold (fp_to_int_sat (ffloor X)) -> (select X == nan, 0, (fcvt X, rdn))

Similar for ceil, trunc, round, and roundeven. This allows us to use
static rounding modes to avoid a libcall.

This is similar to D116771, but for the saturating conversions.

This optimization is done for AArch64 as isel patterns.
RISCV doesn't have instructions for ceil/floor/trunc/round/roundeven
so the operations don't stick around until isel to enable a pattern
match. Thus I've implemented a DAG combine.

I'm only handling saturating to i64 or i32. This could be extended
to other sizes in the future.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D116864