[all-commits] [llvm/llvm-project] 8eae99: [RISCV] Add the zve extension according to the v1....

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8eae99dfe5411707605250d32a735d7b16453a55
      https://github.com/llvm/llvm-project/commit/8eae99dfe5411707605250d32a735d7b16453a55
  Author: eopXD <eop.chen at sifive.com>
  Date:   2022-01-19 (Wed, 19 Jan 2022)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/include/llvm/Support/RISCVISAInfo.h
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/rvv/add.s
    M llvm/test/MC/RISCV/rvv/and.s
    M llvm/test/MC/RISCV/rvv/clip.s
    M llvm/test/MC/RISCV/rvv/compare.s
    M llvm/test/MC/RISCV/rvv/convert.s
    M llvm/test/MC/RISCV/rvv/div.s
    M llvm/test/MC/RISCV/rvv/ext.s
    M llvm/test/MC/RISCV/rvv/fadd.s
    M llvm/test/MC/RISCV/rvv/fcompare.s
    M llvm/test/MC/RISCV/rvv/fdiv.s
    M llvm/test/MC/RISCV/rvv/fmacc.s
    M llvm/test/MC/RISCV/rvv/fminmax.s
    M llvm/test/MC/RISCV/rvv/fmul.s
    M llvm/test/MC/RISCV/rvv/fmv.s
    M llvm/test/MC/RISCV/rvv/fothers.s
    M llvm/test/MC/RISCV/rvv/freduction.s
    M llvm/test/MC/RISCV/rvv/fsub.s
    M llvm/test/MC/RISCV/rvv/invalid-eew.s
    M llvm/test/MC/RISCV/rvv/load.s
    M llvm/test/MC/RISCV/rvv/macc.s
    M llvm/test/MC/RISCV/rvv/mask.s
    M llvm/test/MC/RISCV/rvv/minmax.s
    M llvm/test/MC/RISCV/rvv/mul.s
    M llvm/test/MC/RISCV/rvv/mv.s
    M llvm/test/MC/RISCV/rvv/or.s
    M llvm/test/MC/RISCV/rvv/others.s
    M llvm/test/MC/RISCV/rvv/reduction.s
    M llvm/test/MC/RISCV/rvv/shift.s
    M llvm/test/MC/RISCV/rvv/sign-injection.s
    M llvm/test/MC/RISCV/rvv/store.s
    M llvm/test/MC/RISCV/rvv/sub.s
    M llvm/test/MC/RISCV/rvv/vsetvl.s
    M llvm/test/MC/RISCV/rvv/xor.s

  Log Message:
  -----------
  [RISCV] Add the zve extension according to the v1.0 spec

`zve` is the new standard vector extension to specify varying degrees of
vector support for embedding processors. The `zve` extension is related
to the `zvl` extension and other updates that are added in v1.0.

According to https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21,
Clang defines macro `__riscv_v_max_elen`,  `__riscv_v_max_elen_fp` for
`zve` and it can be used by applications that uses the vector extension.

Authored by: Zakk Chen <zakk.chen at sifive.com> @khchen
Co-Authored by: Eop Chen <eop.chen at sifive.com> @eopXD

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D112408