[all-commits] [llvm/llvm-project] b6a7ae: Optimize shift and accumulate pattern in AArch64.

[adriantong1024 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b6a7ae2c5ddc2ea47d0272f42c73672bc4a633cd
      https://github.com/llvm/llvm-project/commit/b6a7ae2c5ddc2ea47d0272f42c73672bc4a633cd
  Author: Adrian Tong <adriantong1024 at gmail.com>
  Date:   2022-01-20 (Thu, 20 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/shift-accumulate.ll

  Log Message:
  -----------
  Optimize shift and accumulate pattern in AArch64.

AArch64 supports unsigned shift right and accumulate. In case we see a
unsigned shift right followed by an OR. We could turn them into a USRA
instruction, given the operands of the OR has no common bits.

Differential Revision: https://reviews.llvm.org/D114405