[all-commits] [llvm/llvm-project] 21c79b: [RISCV] Add patterns to MIR sign-extension removal...

[mohammed-nurulhoque via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 21c79be5d7a388fa1f304412b1a9aba123f8dbde
      https://github.com/llvm/llvm-project/commit/21c79be5d7a388fa1f304412b1a9aba123f8dbde
  Author: Mohammed Nurul Hoque <mohammed.nurulhoque at imgtec.com>
  Date:   2022-01-19 (Wed, 19 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
    M llvm/test/CodeGen/RISCV/sextw-removal.ll

  Log Message:
  -----------
  [RISCV] Add patterns to MIR sign-extension removal pass.

This patch adds a few instruction patterns that generate sign-extended values or propagate them, adding to the pass introduced in https://reviews.llvm.org/D116397

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117465