[all-commits] [llvm/llvm-project] 7f26a1: AMDGPU/GlobalISel: Introduce pseudo to copy sp in ...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f26a1027f0c41b677aece1976286cd14a89020c
      https://github.com/llvm/llvm-project/commit/7f26a1027f0c41b677aece1976286cd14a89020c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-19 (Wed, 19 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences

Arbitrary stack pointers are accessed using MUBUF instructions with
the voffset field, which is interpreted as the swizzled address. We
want to fold fold into the MUBUF form to use the SP in the SGPR
offset, and previously we were special casing the interpretation of
the pointer value if the access memory operand said it was relative to
the stack pointer.

690f5b7a0128a210093e9b217932743ad35b5c5a removed this check, and moved
the DAG path to special casing copies from SGPRs. This is not an
entirely sound approach, since it's still changing the interpretation
of pointer values based the context.

Introduce a new pseudo which corresponds to the wave-to-vector address
transform. This way the memory instruction has consistent semantics
where the incoming pointer is always interpreted as a vector address,
and we're not obligated to optimize into the MUBUF offset-only
addressing mode. The DAG should probably have an equivalent pseudo.

This should fix some correctness issues, and folding this into
addressing modes will be a future optimization patch.


  Commit: b965617ccc36e1d139f9a74047189bc88609f35c
      https://github.com/llvm/llvm-project/commit/b965617ccc36e1d139f9a74047189bc88609f35c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-19 (Wed, 19 Jan 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    A llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

  Log Message:
  -----------
  GlobalISel: Fix assert on unmerge to different element of casted vector

This was failing if a G_UNMERGE_VALUES produced a different element
type than the cast result type.


Compare: https://github.com/llvm/llvm-project/compare/55b702c37b7e...b965617ccc36