[all-commits] [llvm/llvm-project] 6eb8fc: [X86] Add some missing dependency-breaking zero id...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6eb8fc924485facd911b49370f53ab93728b2935
      https://github.com/llvm/llvm-project/commit/6eb8fc924485facd911b49370f53ab93728b2935
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-01-19 (Wed, 19 Jan 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedIceLake.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/lib/Target/X86/X86ScheduleSLM.td
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td
    M llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s
    M llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s
    M llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s
    M llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s
    M llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s
    M llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s
    M llvm/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/Broadwell/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/Haswell/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/SLM/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/SandyBridge/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/Znver1/zero-idioms.s
    M llvm/test/tools/llvm-mca/X86/Znver2/zero-idioms.s

  Log Message:
  -----------
  [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models

Many of the x86 scheduler models are not accounting for their microarch's ability to handle dependency-breaking zero idioms (pxor xmm0,xmm0 etc.), which is causing some notable differences when comparing llvm-mca reports to iaca, uops.info etc.

These are based on the Intel AoMs and Agner's docs which list the instructions handled on each cpu model - there may be more, although tbh the xor/pxor/xorps/xorpd are by far the most commonly encountered.

Once this is in place we also need to review missing support for 'allones' idioms and reg-reg move elimination, but this needs fixing first.

@lebedev.ri The Barcelona test changes are due to the cpu still being tagged as using the SandyBridge model, if/when you get back to D63628 these will need to be addressed.

Based on an original patch by @andreadb (Andrea Di Biagio)

Differential Revision: https://reviews.llvm.org/D117497