[all-commits] [llvm/llvm-project] 5a6c62: [RISCV] Remove special case for constant shift amo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5a6c622afdff2c18d82dbe4f463450feaa8b7e5e
      https://github.com/llvm/llvm-project/commit/5a6c622afdff2c18d82dbe4f463450feaa8b7e5e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

  Log Message:
  -----------
  [RISCV] Remove special case for constant shift amount in FSHL/FSHR lowering to FSL/FSR.

Remove fshl/fshr with constant shift amount isel patterns. Replace
with fsr/fsl with constant isel patterns.

This hack was trying to preserve as much optimization opportunity
for fshl/fshr by constant as possible, but the conversion to
RISCVISD::FSR/FSL happens so late it probably isn't worth much.

The new isel patterns are needed by D117468 anyway.