[all-commits] [llvm/llvm-project] b3a0ec: [RISCV] Remove DemandedBits handling for FSR/FSL u...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b3a0ec7645dbd2978bd43f372933d1d1cd36f132
      https://github.com/llvm/llvm-project/commit/b3a0ec7645dbd2978bd43f372933d1d1cd36f132
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Remove DemandedBits handling for FSR/FSL until we have test cases for it.

Testing may be easier after D117468. Right now we get demanded bits
optimizations done on ISD::FSHL/FSHR before they become FSR/FSL. This
makes it hard to test.


  Commit: aa7fc02febec17ebc1fd46934ac0c90d31969d5d
      https://github.com/llvm/llvm-project/commit/aa7fc02febec17ebc1fd46934ac0c90d31969d5d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

  Log Message:
  -----------
  Recommit "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."

This reverts the revert commit e32838573929ac85fc4df3058593798d10ce4cd2.

Accidental demanded bits change has been removed. The demanded bits
code itself was remove in a pre-commit since it isn't tested.

Original commit message:
Previous we used the fshl/fshr operand ordering for simplicity. This
made things confusing when D117468 proposed adding intrinsics for
the instructions. We can't just use the generic funnel shifting
intrinsics because fsl/fsr have different functionality that should
be exposed to software.

Now we use rs1, rs3, rs2/shamt order which matches the instruction
printing order and the order used in this intrinsic header
https://github.com/riscv/riscv-bitmanip/blob/main-history/cproofs/rvintrin.h


Compare: https://github.com/llvm/llvm-project/compare/de1600a1d946...aa7fc02febec