[all-commits] [llvm/llvm-project] e32838: Revert "[RISCV] Make the operand order for RISCVIS...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e32838573929ac85fc4df3058593798d10ce4cd2
      https://github.com/llvm/llvm-project/commit/e32838573929ac85fc4df3058593798d10ce4cd2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

  Log Message:
  -----------
  Revert "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."

This reverts commit b634f8a663d56877663f5224a785d9f0263c4176.

I broke the SimplifyDemandedBits code, but we don't have tests.