[all-commits] [llvm/llvm-project] b634f8: [RISCV] Make the operand order for RISCVISD::FSL(W...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b634f8a663d56877663f5224a785d9f0263c4176
      https://github.com/llvm/llvm-project/commit/b634f8a663d56877663f5224a785d9f0263c4176
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

  Log Message:
  -----------
  [RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering.

Previous we used the fshl/fshr operand ordering for simplicity. This
made things confusing when D117468 proposed adding intrinsics for
the instructions. We can't just use the generic funnel shifting
intrinsics because fsl/fsr have different functionality that should
be exposed to software.

Now we use rs1, rs3, rs2/shamt order which matches the instruction
printing order and the order used in this intrinsic header
https://github.com/riscv/riscv-bitmanip/blob/main-history/cproofs/rvintrin.h