[all-commits] [llvm/llvm-project] 2e2132: [InstCombine] add tests for fsub with fmul/fdiv op...

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2e21327033cebb1e28d7a23cbb2e3dda493b5c45
      https://github.com/llvm/llvm-project/commit/2e21327033cebb1e28d7a23cbb2e3dda493b5c45
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/test/Transforms/InstCombine/fsub.ll

  Log Message:
  -----------
  [InstCombine] add tests for fsub with fmul/fdiv operand; NFC


  Commit: 2d50630efbc427bec0028578f7639dc38e928bbb
      https://github.com/llvm/llvm-project/commit/2d50630efbc427bec0028578f7639dc38e928bbb
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp

  Log Message:
  -----------
  [InstCombine] reduce code duplication; NFC


  Commit: 870591200dc83e2ed4b4f6cf4ec03074d0d1a084
      https://github.com/llvm/llvm-project/commit/870591200dc83e2ed4b4f6cf4ec03074d0d1a084
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  Log Message:
  -----------
  [SDAG] remove duplicate functionality when getting shift type for demanded bits; NFCI

This was noted as a potential cleanup in D117508.
getShiftAmountTy() has checks for vector, phase, etc. so it should
handle anything that the caller was trying to account for.


Compare: https://github.com/llvm/llvm-project/compare/4fae93298763...870591200dc8