[all-commits] [llvm/llvm-project] 5ceb4f: [RISCV] Add instruction schedule for Zbc extension...

[WangLian via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ceb4f5446f38ee81e74cd6ab9dd003c6d94280d
      https://github.com/llvm/llvm-project/commit/5ceb4f5446f38ee81e74cd6ab9dd003c6d94280d
  Author: Lian Wang <Lian.Wang at streamcomputing.com>
  Date:   2022-01-18 (Tue, 18 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleB.td

  Log Message:
  -----------
  [RISCV] Add instruction schedule for Zbc extension and Zbs extension

Zbc extension:
CLMUL/CLMULR/CLMULH are grouped together, defined one schedule class.

Zbs extension:
BCLR/BSET/BINV/BEXT are grouped together, defined one schedule class.
BCLRI/BSETI/BINVI/BEXTI are grouped together, defined one schedule class.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117538