[all-commits] [llvm/llvm-project] 3fc4b5: [RISCV] Make SplatOperand start from 0.

[Han-Kuan Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3fc4b5896a336b5b74c52bbde992992aeb5a78f0
      https://github.com/llvm/llvm-project/commit/3fc4b5896a336b5b74c52bbde992992aeb5a78f0
  Author: Han-Kuan Chen <hankuan.chen at sifive.com>
  Date:   2022-01-17 (Mon, 17 Jan 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h

  Log Message:
  -----------
  [RISCV] Make SplatOperand start from 0.

Current SplatOperand starts from 1 because operand 0 (or 1) is intrinsic
id in SelectionDAG.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117453


  Commit: ec9cb3a79cd648a731cd9033447123c216da5297
      https://github.com/llvm/llvm-project/commit/ec9cb3a79cd648a731cd9033447123c216da5297
  Author: Han-Kuan Chen <hankuan.chen at sifive.com>
  Date:   2022-01-17 (Mon, 17 Jan 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

  Log Message:
  -----------
  [RISCV] Provide VLOperand in td.

Currently, users expected VL is the last operand. However, since some
intrinsics has tail policy in the last operand, this rule cannot be used
anymore.

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D117452


Compare: https://github.com/llvm/llvm-project/compare/c29d6c410e76...ec9cb3a79cd6