[all-commits] [llvm/llvm-project] ba6485: [SDAG] add demanded bits transform for bswap

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ba6485e25fc56468f34cc8a6938d66d3c5f46596
      https://github.com/llvm/llvm-project/commit/ba6485e25fc56468f34cc8a6938d66d3c5f46596
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-01-17 (Mon, 17 Jan 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/bswap-known-bits.ll
    M llvm/test/CodeGen/X86/combine-bswap.ll

  Log Message:
  -----------
  [SDAG] add demanded bits transform for bswap

A possible codegen regression for PowerPC is noted in D117406
because we don't recognize a pattern that demands only 1 byte
from a bswap.

This fold  has existed in IR since close to the beginning of LLVM:
https://github.com/llvm/llvm-project/blame/main/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L794
...so this patch copies that code as much as possible and adapts
it for SDAG.

The test for PowerPC that would change in D117406 is over-reduced
with undefs, so I recreated it for AArch64 and x86 by passing in
pointer args and renamed the values to make the logic clearer.

Differential Revision: https://reviews.llvm.org/D117508