[all-commits] [llvm/llvm-project] cc3516: [RISCV] Add initial support for getRegUsageForType...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc35161dc716ab5b0e66b15ac320ebd451a2bc44
      https://github.com/llvm/llvm-project/commit/cc35161dc716ab5b0e66b15ac320ebd451a2bc44
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-01-17 (Mon, 17 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll

  Log Message:
  -----------
  [RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters

Those two TTI hooks are used during vectorization for calculating
register pressure, the default implementation isn't consider for LMUL,
and that's also definitly wrong value for register number (all register class
are 8 registers).

So in this patch we tried to:

1. Calculate right register usage for vector type and scalar type.
2. Return right number of register for general purpose register and
   vector register.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D116890