[all-commits] [llvm/llvm-project] f00a98: [RISCV] Add CSRs defined in the recently ratified ...

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f00a98a0a90e80f9790e6b505f5a5d4d64741690
      https://github.com/llvm/llvm-project/commit/f00a98a0a90e80f9790e6b505f5a5d4d64741690
  Author: Alex Bradbury <asb at lowrisc.org>
  Date:   2022-01-15 (Sat, 15 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/MC/RISCV/rv32-machine-csr-names.s
    M llvm/test/MC/RISCV/rv32-only-csr-names.s
    M llvm/test/MC/RISCV/supervisor-csr-names.s

  Log Message:
  -----------
  [RISCV] Add CSRs defined in the recently ratified Sscofpmf extension

The "RISC-V Count Overflow and Mode-Based Filtering Extension" was
ratified at the end of last year though hasn't yet been integrated in
the main specification documents (see
<https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions>).

This commit adds the CSRs defined by this extension in
<https://github.com/riscv/riscv-count-overflow/releases/download/v0.5.2/Sscofpmf.pdf>.

Differential Revision: https://reviews.llvm.org/D117308


  Commit: 1ca79823e0562be2a065377dda1474b0dc9c9e4d
      https://github.com/llvm/llvm-project/commit/1ca79823e0562be2a065377dda1474b0dc9c9e4d
  Author: Alex Bradbury <asb at lowrisc.org>
  Date:   2022-01-15 (Sat, 15 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/MC/RISCV/hypervisor-csr-names.s
    M llvm/test/MC/RISCV/machine-csr-names.s
    M llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
    M llvm/test/MC/RISCV/rv32-machine-csr-names.s
    M llvm/test/MC/RISCV/rv32-only-csr-names.s
    M llvm/test/MC/RISCV/supervisor-csr-names.s

  Log Message:
  -----------
  [RISCV] Add CSRs defined in the recently ratified Smstateen extension

The "RISC-V State Enable Extension" was ratified at the end of at the
end of last year though hasn't yet been integrated in the main
specification documents (see
<https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions>).

This commit adds the CSRs defined by this extension in
<https://github.com/riscv/riscv-state-enable/releases/download/v0.6.3/Smstateen.pdf>.

Differential Revision: https://reviews.llvm.org/D117310


  Commit: 0ee679e22cfba9dfd5f6d07e7ff9687192419034
      https://github.com/llvm/llvm-project/commit/0ee679e22cfba9dfd5f6d07e7ff9687192419034
  Author: Alex Bradbury <asb at lowrisc.org>
  Date:   2022-01-15 (Sat, 15 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/MC/RISCV/hypervisor-csr-names.s
    M llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
    M llvm/test/MC/RISCV/rv32-only-csr-names.s
    A llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
    M llvm/test/MC/RISCV/supervisor-csr-names.s

  Log Message:
  -----------
  [RISCV] Add CSRs defined in the recently ratified Sstc extension

The 'RISC-V "stimecmp / vstimecmp" Extension' was ratified at the end of
last year though hasn't yet been integrated in the main specification
documents (see
<https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions>).

RISC-V "stimecmp / vstimecmp" Extension
<https://github.com/riscv/riscv-time-compare/releases/download/v0.5.4/Sstc.pdf>.

Differential Revision: https://reviews.llvm.org/D117311


Compare: https://github.com/llvm/llvm-project/compare/2e589c9c4233...0ee679e22cfb