[all-commits] [llvm/llvm-project] ac6b48: [RISCV] Honor the VT when converting float point r...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac6b4896ea910797203f04972c2cd0e157692f7d
      https://github.com/llvm/llvm-project/commit/ac6b4896ea910797203f04972c2cd0e157692f7d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-14 (Fri, 14 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
    M llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

  Log Message:
  -----------
  [RISCV] Honor the VT when converting float point register names to register class for inline assembly.

It appears the code here was written for the inline asm clobbering
a specific register, but it also gets used for named input and
output registers.

For the input and output case, we should honor the VT so we
don't insert conversion instructions around the inline assembly.

For the clobber, case we need to pick the largest register class.

Reviewed By: asb, jrtc27

Differential Revision: https://reviews.llvm.org/D117279