[all-commits] [llvm/llvm-project] bea16e: [mlir] Fix invalid assertion in ModuleTranslation.cpp

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bea16e72a757fc72b9237098606ead945377170f
      https://github.com/llvm/llvm-project/commit/bea16e72a757fc72b9237098606ead945377170f
  Author: Alex Zinenko <zinenko at google.com>
  Date:   2022-01-14 (Fri, 14 Jan 2022)

  Changed paths:
    M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
    M mlir/test/Target/LLVMIR/llvmir.mlir

  Log Message:
  -----------
  [mlir] Fix invalid assertion in ModuleTranslation.cpp

LLVM dialect supports terminators with repeated successor blocks that take
different operands. This cannot be directly expressed in LLVM IR though since
it uses the number of the predecessor block to differentiate values in its PHI
nodes. Therefore, the translation to LLVM IR inserts dummy blocks to forward
arguments in case of repeated succesors with arguments. The insertion works
correctly. However, when connecting PHI nodes to their source values, the
assertion of the insertion having worked correctly was incorrect: it would only
trigger if repeated blocks were adjacent in the successor list (not guaranteed
by anything) and would not check if the successors have operands (no need for
dummy blocks in absence of operands since no PHIs are being created). Change
the assertion to only trigger in case of duplicate successors with operands,
and don't expect them to be adjacent.

Reviewed By: wsmoses

Differential Revision: https://reviews.llvm.org/D117214