[all-commits] [llvm/llvm-project] 317452: [RISCV] Add inline asm f32 test cases with D exten...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 317452551683cb4703c0b2af84e41044c9b24f56
      https://github.com/llvm/llvm-project/commit/317452551683cb4703c0b2af84e41044c9b24f56
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll

  Log Message:
  -----------
  [RISCV] Add inline asm f32 test cases with D extension. NFC

Using named registers as input or output constraints creates fcvt.d.s
and fcvt.s.d instructions around the inline assembly.

This makes the data unusable by the inline assembly and corrupts
the results of the inline assembly.


  Commit: d72ebafda001b6e06fc91d1ddeea811b64357e25
      https://github.com/llvm/llvm-project/commit/d72ebafda001b6e06fc91d1ddeea811b64357e25
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

  Log Message:
  -----------
  [RISCV] Add basic Zfh inline assembly tests. NFC

The abi name test shows incorrect fcvt.d.h, fcvt.h.d, fcvt.f.h,
and fcvt.h.f instructions around the inline assembly.


Compare: https://github.com/llvm/llvm-project/compare/0c391133c920...d72ebafda001