[all-commits] [llvm/llvm-project] 37e34b: [LoopInterchange] Enable interchange with multiple...

[CongzheUalberta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 37e34b74e906dab7422ec6e72edf698335b19eca
      https://github.com/llvm/llvm-project/commit/37e34b74e906dab7422ec6e72edf698335b19eca
  Author: Congzhe Cao <congzhe.cao at huawei.com>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
    A llvm/test/Transforms/LoopInterchange/interchangeable-outerloop-multiple-indvars.ll

  Log Message:
  -----------
  [LoopInterchange] Enable interchange with multiple outer loop indvars

This patch enables loop interchange with multiple outer loop
induction variables, and hence removes the limitation that only
a single outer loop induction variable is supported. In fact, it
turns out that the current pass already trivially supports multiple
outer indvars, which is the result of a previous patch
`https://reviews.llvm.org/D102743`. Therefore, this patch removed that
limitation and provides test cases for multiple outer indvars.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D114916