[all-commits] [llvm/llvm-project] a6f494: AMDGPU: Optimize outgoing workitem ID based on req...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a6f49423c1ecad4b414c204822d26d9025da2599
      https://github.com/llvm/llvm-project/commit/a6f49423c1ecad4b414c204822d26d9025da2599
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll

  Log Message:
  -----------
  AMDGPU: Optimize outgoing workitem ID based on reqd_work_group_size

If we know we we aren't using a component from the kernel, we can save
a few bit packing instructions.

We're still enabling the VGPR input to the kernel though.


  Commit: 59994c25f9df9db598c48fd33d8c3089b45184cd
      https://github.com/llvm/llvm-project/commit/59994c25f9df9db598c48fd33d8c3089b45184cd
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll

  Log Message:
  -----------
  AMDGPU: Select workitem ID intrinsics to 0 with req_work_group_size

Shockingly we weren't doing this already. We should probably have this
be done earlier in the IR too, but it's still helpful to have the
lowering guarantee it so that we can modify the ABI implicit inputs
based on it.


Compare: https://github.com/llvm/llvm-project/compare/c719a8596d01...59994c25f9df