[all-commits] [llvm/llvm-project] f41394: [Docs] Fix IR and TableGen grammar inconsistencies

[Sebastian Neubauer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f4139440f1cf2b30705d7f81104cc51eca3d4977
      https://github.com/llvm/llvm-project/commit/f4139440f1cf2b30705d7f81104cc51eca3d4977
  Author: Sebastian Neubauer <Sebastian.Neubauer at amd.com>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/docs/TableGen/ProgRef.rst
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp

  Log Message:
  -----------
  [Docs] Fix IR and TableGen grammar inconsistencies

IR:
- globals (and functions, ifuncs, aliases) can have a partition
- catchret has a `to` before the label
- the sint/int types do not exist
- signext comes after the type
- a variable was missing its type

TableGen:
- The second value after a `#` concatenation is optional
  See e.g. llvm/lib/Target/X86/X86InstrAVX512.td:L3351
- IncludeDirective and PreprocessorDirective were never referenced in
  the grammar
- Add some missing ;
- Parent classes of multiclasses can have generic arguments.
  Reuse the `ParentClassList` that is already used in other places.

MIR:
- liveins only allows physical registers, which start with a $

Differential Revision: https://reviews.llvm.org/D116674