[all-commits] [llvm/llvm-project] 31009f: [CodeGen][AArch64] Ensure isSExtCheaperThanZExt re...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 31009f0b5afb504fc1f30769c038e1b7be6ea45b
      https://github.com/llvm/llvm-project/commit/31009f0b5afb504fc1f30769c038e1b7be6ea45b
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/CodeGenPrepare.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
    M llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
    M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
    M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
    M llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
    M llvm/test/CodeGen/AArch64/funnel-shift.ll
    M llvm/test/CodeGen/AArch64/reduce-and.ll
    M llvm/test/CodeGen/AArch64/redundant-copy-elim-empty-mbb.ll
    M llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
    M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
    M llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll

  Log Message:
  -----------
  [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

When we know the value we're extending is a negative constant then it
makes sense to use SIGN_EXTEND because this may improve code quality in
some cases, particularly when doing a constant splat of an unpacked vector
type. For example, for SVE when splatting the value -1 into all elements
of a vector of type <vscale x 2 x i32> the element type will get promoted
from i32 -> i64. In this case we want the splat value to sign-extend from
(i32 -1) -> (i64 -1), whereas currently it zero-extends from
(i32 -1) -> (i64 0xFFFFFFFF). Sign-extending the constant means we can use
a single mov immediate instruction.

New tests added here:

  CodeGen/AArch64/sve-vector-splat.ll

I believe we see some code quality improvements in these existing
tests too:

  CodeGen/AArch64/dag-numsignbits.ll
  CodeGen/AArch64/reduce-and.ll
  CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll

The apparent regressions in CodeGen/AArch64/fast-isel-cmp-vec.ll only
occur because the test disables codegen prepare and branch folding.

Differential Revision: https://reviews.llvm.org/D114357