[all-commits] [llvm/llvm-project] d04382: [AMDGPU] Fixed physreg asm constraint parsing

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d043822daab9b4e7176a48c6794cb454e7398ec0
      https://github.com/llvm/llvm-project/commit/d043822daab9b4e7176a48c6794cb454e7398ec0
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  Log Message:
  -----------
  [AMDGPU] Fixed physreg asm constraint parsing

We are always failing parsing of the physreg constraint because
we do not drop trailing brace, thus getAsInteger() returns a
non-empty string and we delegate reparsing to the TargetLowering.

In addition it did not parse register tuples.

Fixed which has allowed to remove w/a in two places we call it.

Differential Revision: https://reviews.llvm.org/D117055