[all-commits] [llvm/llvm-project] 07ddfa: GlobalISel: Add G_ASSERT_ALIGN hint instruction

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jan 12 15:57:47 PST 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 07ddfa95e3b5ea8464e90545f592624221b854ae
      https://github.com/llvm/llvm-project/commit/07ddfa95e3b5ea8464e90545f592624221b854ae
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

  Log Message:
  -----------
  GlobalISel: Add G_ASSERT_ALIGN hint instruction

Insert it for call return values only for now, which is the only case
the DAG handles also.


  Commit: 3d2d208f6a0a421b23937c39b9d371183a5913a3
      https://github.com/llvm/llvm-project/commit/3d2d208f6a0a421b23937c39b9d371183a5913a3
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M llvm/include/llvm/IR/InstrTypes.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll

  Log Message:
  -----------
  IR: Make getRetAlign check callee function attributes

The attribute queries semi-consistently check the attribute set, and
then fallback to checking the callee's attributes.


  Commit: ab593baa2dc1361b0d82fec13487ae0393e0908d
      https://github.com/llvm/llvm-project/commit/ab593baa2dc1361b0d82fec13487ae0393e0908d
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll

  Log Message:
  -----------
  AMDGPU: Add base test for future optimization patch


  Commit: 4515c24bbc32196957b03c6a42259d460c9c4848
      https://github.com/llvm/llvm-project/commit/4515c24bbc32196957b03c6a42259d460c9c4848
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix assertions on legalize queries with huge align

For some reason we pass around the alignment in bits as uint64_t. Two
places were truncating it to unsigned, and losing bits in extreme
cases.


  Commit: 5f39a02ea950dbbc146f2e22a7a51e5dea430ce6
      https://github.com/llvm/llvm-project/commit/5f39a02ea950dbbc146f2e22a7a51e5dea430ce6
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M llvm/lib/CodeGen/RegisterScavenging.cpp

  Log Message:
  -----------
  RegScavenger: Remove used regs from scavenge candidates

In a future change, AMDGPU will have 2 emergency scavenging indexes in
some situations. The secondary scavenging index ends up being used
recursively when the scavenger calls eliminateFrameIndex for the
emergency spill slot. Without this, it would end up seeing the same
register which was just scavenged in the parent call as free, inserts
a second emergency spill to the same location and returns the same
register when 2 unique free registers are required.

We need to only do this if the register is used. SystemZ uses 2
scavenging slots, but calls the scavenger twice in sequence and not
recursively. In this case the previously scavenged register can be
re-clobbered, but is still tracked in the scavenger until it sees the
deferred restore instruction.


  Commit: 5a16306c094489b2fa295899f80bb8413bd92a2a
      https://github.com/llvm/llvm-project/commit/5a16306c094489b2fa295899f80bb8413bd92a2a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
    M llvm/test/CodeGen/AArch64/O0-pipeline.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir

  Log Message:
  -----------
  GlobalISel: Always enable GISelKnownBits for InstructionSelect

This wasn't running at -O0, and causing crashes for AMDGPU. AMDGPU
needs this to match the addressing modes of stack access instructions,
which is even more important at -O0 than with optimizations.

It currently costs nothing to run ahead of time, so just always enable
it.


Compare: https://github.com/llvm/llvm-project/compare/9be193bc58b3...5a16306c0944


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