[all-commits] [llvm/llvm-project] be1cc6: [RISCV] Add DAG combine to fold (fp_to_int (ffloor...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: be1cc64cc13cb24bcd9ed097925a140d74beaa45
      https://github.com/llvm/llvm-project/commit/be1cc64cc13cb24bcd9ed097925a140d74beaa45
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-11 (Tue, 11 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/double-round-conv.ll
    A llvm/test/CodeGen/RISCV/float-round-conv.ll
    A llvm/test/CodeGen/RISCV/half-round-conv.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)

Similar for ceil, trunc, round, and roundeven. This allows us to use
static rounding modes to avoid a libcall.

This optimization is done for AArch64 as isel patterns.
RISCV doesn't have instructions for ceil/floor/trunc/round/roundeven
so the operations don't stick around until isel to enable a pattern
match. Thus I've implemented a DAG combine.

We only handle XLen types except i32 on RV64. i32 will be type
legalized to a RISCVISD node. All other types will be type legalized
to XLen and maintain the FP_TO_SINT/UINT ISD opcode.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D116771